The present invention relates to a semiconductor integrated circuit technique and, further, to a command control method for use in a semiconductor integrated circuit having therein a plurality of memory circuits. The invention relates to a technique which is effective for use in, for example, enabling repair of a defective bit and in the adjustment of the operation timing of a circuit after a chip is mounted.
Hitherto, in a semiconductor integrated circuit having therein a semiconductor memory, such as a RAM (Random Access Memory) or a memory circuit, in order to improve the yield by repairing a defective bit (defective memory cell) included in a memory array, a redundancy circuit, such as an address setting circuit for storing a spare memory column, a spare memory row and a defect address, is provided. A defect address in such a redundancy circuit is generally set by using a programmable fuse activated by a laser or the like.
In a repairing method involving the steps of blowing a fuse using a laser to store defect address information, comparing an input address with the stored defect address information, and replacing a defective memory row or a defective memory column with a spare memory row or a spare memory column, a fuse has to be blown before the memory chip is sealed in a package. A defect occurring after the memory chip is sealed in the package cannot be repaired, and this causes a problem in that a sufficiently improved yield cannot be achieved.
A technique in which a nonvolatile memory, such as an EEPROM (Electrically Erasable Programmable Read Only Memory), is provided in a chip of a DRAM (Dynamic Random Access Memory) for storing defect address information, has been proposed. According to such a technique, even after a chip is sealed in a package, defect address information can be written into the EEPROM. Consequently, a defect occurring after the chip is sealed in the package can be repaired, so that the yield can be improved.
It was, however, clarified by examination of the inventor of the present invention that the conventionally proposed repairing method using an EEPROM has the following problems. Although defect address information can be written in the EEPROM even after the chip is sealed in the package, in a state where the chip is mounted on a printed wiring board (hereinbelow, called a board), a module, or the like, the defect address information cannot be written. A new control terminal for writing information to the EEPROM and a source terminal for applying a high voltage necessary for writing/erasing information to/from the EEPROM are necessary, and so compatibility with a conventional memory cannot be maintained. The memory repairing method is disclosed in Japanese Unexamined Patent Application Laid-Open No. Hei 8(1996)-31196 and Japanese Patent Application No. Hei 11(1999)-23631 (corresponding to U.S. application Ser. No. 09/493280).
An object of the invention is to provide a semiconductor integrated circuit having therein a memory circuit, such as a RAM, in which defect address information can be easily written even in a state where a chip is sealed in a package and is further mounted on a board, module, or the like, thereby making it possible to repair a defective bit in the memory circuit and accordingly achieve an improved yield.
Another object of the invention is to provide a semiconductor integrated circuit having therein a memory circuit such as a RAM, in which the operation timing of the circuit is adjusted to increase the operation margin, thereby enabling the circuit to operate at higher speed.
Still another object of the invention is to provide a semiconductor integrated circuit in which a chip can be prevented from losing compatibility with a conventional chip due to an increase in the number of terminals or a different pin arrangement.
The foregoing objects of the invention, other objects, and novel features will become apparent from the description of the specification and the attached drawings.
The outline of representative aspects and features of the invention disclosed in this application will be described as follows.
In a semiconductor integrated circuit comprising: a first storage (11) having a memory cell of a first configuration; a second storage (20) having a memory cell of a second configuration; a plurality of control terminals for receiving a plurality of control signals from the outside; and a plurality of address terminals for receiving a plurality of address signals for selecting a memory cell in the first storage, an operation of the first storage is instructed according to a first combination (CS, RAS, CAS, and WE=xe2x80x9cLxe2x80x9d, and A7=xe2x80x9c0xe2x80x9d) of the signals (CS, RAS, CAS, and WE) supplied to the control terminals and at least a part (A7) of the signals supplied to the address terminals, and an operation of the second storage is instructed according to a second combination (CS, RAS, CAS, and WE=xe2x80x9cLxe2x80x9d, and A7=xe2x80x9c1xe2x80x9d) of the signals supplied to the control terminals and at least a part of the signals supplied to the address terminals.
According to the above, the first and second storages having memory cells of different configurations can be accessed by the same command. Consequently, the first and second storages can be separately operated without providing a new external control terminal.
Desirably, the signals supplied to the control terminals in the first combination and those in the second combination are the same, and a signal supplied to the address terminal in the first combination and that in the second combination are different from each other. Consequently, by the signal supplied to the address terminal, the instruction to the first storage and the instruction to the second storage by the same command can be discriminated from each other. Thus, the first and second storages can be operated separately without providing a new external terminal.
In a semiconductor integrated circuit comprising: a first storage having a memory cell of a first configuration; a second storage having a memory cell of a second configuration; a plurality of control terminals for receiving a plurality of control signals from the outside; and a plurality of address terminals for receiving a plurality of address signals for selecting a memory cell in the first storage, a command for instructing an operation of the first storage, which is specified by a combination of the control signals supplied to the control terminals after the operation of the first storage or the operation of the second storage is instructed and a command for instructing the operation of the second storage are the same code. With this configuration, while effectively using the combinations of a relatively small number of control signals, the first and second storages can be operated separately.
Further, in a semiconductor integrated circuit comprising: a first storage having a memory cell of a first configuration; a second storage having a memory cell of a second configuration; a plurality of control terminals for receiving a plurality of control signals from the outside; and a plurality of address terminals for receiving a plurality of address signals for selecting a memory cell in the first storage, an operation of the first storage is instructed according to a first combination of the signals supplied to the control terminals and at least a part of the signals supplied to the address terminals, an operation of the second storage is instructed according to a second combination of the signals supplied to the control terminals and at least a part of the signals supplied to the address terminals, and a command for instructing an operation of the first storage, which is specified by a combination of the control signals supplied to the control terminals after the operation of the first storage or the operation of the second storage is instructed and a command for instructing the operation of the second storage are the same code.
Consequently, since the first and second storages having memory cells of different configurations can be accessed by the same command, the first and second storages can be operated separately without providing a new external control terminal, and the first and second storages can be operated separately while effectively using combinations of a relatively small number of control signals.
In this case as well, desirably, the signals supplied to the control terminals in the first combination and those in the second combination are the same, and the signal (s) supplied to the address terminals) in the first combination and that (those) in the second combination are different from each other. Since the instruction to the first storage and that to the second storage by the same command can be discriminated from each other by the signal supplied to the address terminal, the first and second storages can be operated separately without providing a new external terminal.
Further, preferably, information stored in the second storage is defect address information of the first storage. Since the first an) second storages can be accessed by the same command, even after the chip is sealed in package or mounted on a board, a defect can be repaired and the yield is accordingly improved.
Information stored in the second storage is information regarding an operation timing of the first storage. Consequently, even after the chip is sealed in a package, the operation timing of the circuit can be adjusted. Thus, the yield is further improved and the performances of the circuit can be improved.
Further, when the memory cell of the second configuration is a nonvolatile memory cell, a booster circuit for increasing a normal source voltage to thereby generate a high voltage to be used at the time of writing data to the nonvolatile memory is provided. It becomes unnecessary to newly provide an external terminal for applying a high voltage necessary for writing.
At the time of writing or erasing data to/from the nonvolatile memory, the time necessary for the writing or erasing operation is determined by the number of repetitions of a command which does not generate a new operation. Consequently, data can be written to the nonvolatile memory with reliability without newly providing a timer or the like.
Further, in the case where a mode register for setting an operation mode designated by a signal supplied from the outside is provided, a command determined by signals supplied to the control terminals in the first combination or the second combination is a command for instructing setting of a mode to the mode register. Thus, the first and second storages can be operated separately by using an existing command without newly providing an external control terminal.
Further, in a system in which a first semiconductor device and a second semiconductor device which can access a storage included in the first semiconductor device are mounted on a single printed wiring board, the storage includes a volatile memory and a nonvolatile memory, the first semiconductor device further comprises: a plurality of first input terminals for receiving a plurality of control signals; and a plurality of second input terminals for receiving a plurality of address signals, each of a first command for controlling the volatile memory and a second command for controlling the nonvolatile memory is specified by signals supplied to the plurality of first input terminals and signal (s) supplied to one or more of the plurality of second input terminals, and a combination of the plurality of control signals is common to the first command and the second command, and the signal(s) supplied to one or more of the plurality of second input terminals for the first command and that (those) for the second command are different from each other.
With this configuration, also after the semiconductor integrated circuit is mounted on a board, such as a printed wiring board or a module, the defect address information or the timing adjustment information of the first storage can be written to the second storage. Thus, the reliability and performance of the system can be increased.